Integrated chip package structure using organic substrate and method of manufacturing the same

ABSTRACT

An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority benefit of Taiwanapplication serial No. 90133093, filed Dec. 31, 2001.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to an integrated chip packagestructure and method of manufacture the same. More particularly, thepresent invention relates to an integrated chip package structure andmethod of manufacture the same using organic substrate.

[0004] 2. Description of Related Art

[0005] In the recent years, the development of advanced technology is onthe cutting edge. As a result, high-technology electronics manufacturingindustries launch more feature-packed and humanized electronic productsThese new products that hit the showroom are lighter, thinner, andsmaller in design. In the manufacturing of these electronic products,the key component has to be the integrated circuit (IC) chip inside anyelectronic product.

[0006] The operability, performance, and life of an IC chip are greatlyaffected by its circuit design, wafer manufacturing, and chip packaging.For this present invention, the focus will be on chip packagingtechnique. Since the features and speed of IC chips are increasingrapidly, the need for increasing the conductivity of the circuitry isnecessary so that the signal delay and attenuation of the dies to theexternal circuitry are reduced. A chip package that allows good thermaldissipation and protection of the IC chips with a small overalldimension of the package is also necessary for higher performance chips.These are the goals to be achieved in chip packaging.

[0007] There are a vast variety of existing chip package techniques suchas ball grid array (BGA), wire bonding, flip chip, etc . . . formounting a die on a substrate via the bonding points on both the die andthe substrate. The inner traces helps to fan out the bonding points onthe bottom of the substrate. The solder balls are separately planted onthe bonding points for acting as an interface for the die toelectrically connect to the external circuitry. Similarly, pin gridarray (PGA) is very much like BGA, which replaces the balls with pins onthe substrate and PGA also acts an interface for the die to electricallyconnect to the external circuitry.

[0008] Both BGA and PGA packages require wiring or flip chip formounting the die on the substrate. The inner traces in the substrate fanout the bonding points on the substrate, and electrical connection tothe external circuitry is carried out by the solder balls or pins on thebonding points. As a result, this method fails to reduce the distance ofthe signal transmission path but in fact increase the signal pathdistance. This will increase signal delay and attenuation and decreasethe performance of the chip.

[0009] Wafer level chip scale package (WLCSP) has an advantage of beingable to print the redistribution circuit directly on the die by usingthe peripheral area of the die as the bonding points It is achieved byredistributing an area array on the surface of the die, which can fullyutilize the entire area of the die. The bonding points are located onthe redistribution circuit by forming flip chip bumps so the bottom sideof the die connects directly to the printed circuit board (PCB) withmicro-spaced bonding points.

[0010] Although WLCSP can greatly reduce the signal path distance, it isstill very difficult to accommodate all the bonding points on the diesurface as the integration of die and internal components gets higher.The pin count on the die increases as integration gets higher so theredistribution of pins in an area array is difficult to achieve. Even ifthe redistribution of pins is successful, the distance between pins willbe too small to meet the pitch of a printed circuit board (PCB).

SUMMARY OF THE INVENTION

[0011] Therefore the present invention provides an integrated chippackage structure and method of manufacturing the same that uses theoriginal bonding points of the die and connect them to an externalcircuitry of a thin-film circuit layer to achieve redistribution. Thespacing between the redistributed bonding points matches the pitch of aPCB.

[0012] In order to achieve the above object, the present inventionpresents an integrated chip package structure and method ofmanufacturing the same by adhering the backside of a die to an organicsubstrate, wherein the active surface of the die has a plurality ofmetal pads. A thin-film circuit layer is formed on top of the die andthe organic substrate, where the thin-film circuit layer has an externalcircuitry that is electrically connected to the metal pads of the die.The external circuitry extends to a region that is outside the activearea of the dies and has a plurality of bonding pads located on thesurface of the thin-film layer circuit. The active surface of the diehas an internal circuitry and a plurality of active devices, wheresignals can be transmitted from one active device to the externalcircuitry via the internal circuitry, then from the external circuitryback to another active device via the internal circuitry. Furthermore,the organic substrate has at least one inwardly protruded area so thebackside of the die can be adhered inside the inwardly protruded areaand exposing the active surface of the die. Wherein the organicsubstrate is composed of an organic layer and a heat conducting materialformed overlapping and the inwardly protruded areas are formed byoverlapping the organic substrate with openings on the heat conductinglayer. Furthermore, the present chip package structure allows multipledies with same or different functions to be packaged into one integratedchip package and permits electrically connection between the dies by theexternal circuitry.

[0013] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary, andare intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings,

[0015]FIGS. 1A to 1I are schematic diagrams showing the sectional viewof the structure of the first embodiment of the present invention.

[0016]FIGS. 2A to 2C are schematic diagrams showing the sectional viewof the structure of the second embodiment of the present invention.

[0017]FIGS. 2D to 2E are schematic diagrams showing the sectional viewof the formation of inwardly protruded areas in the organic substrate ofthe structure of the second embodiment of the present invention.

[0018]FIGS. 3A to 3C are schematic diagrams showing the sectional viewof the structure of the third embodiment of the present invention.

[0019]FIGS. 4A to 4I are schematic diagrams showing the sectional viewof the structure of the forth embodiment of the present invention.

[0020]FIGS. 5A to 5E are schematic diagrams showing the sectional viewof the structure of the fifth embodiment of the present invention.

[0021]FIG. 6 is a schematic diagram showing the section view of the chippackage structure of a preferred embodiment of the present inventionwith one die.

[0022]FIG. 7 is a schematic diagram showing the section view of the chippackage structure of a preferred embodiment of the present inventionwith a plurality of dies.

[0023]FIG. 8 is a magnified diagram showing the sectional view of thechip package structure of a preferred embodiment of the presentinvention.

[0024]FIGS. 9A, 9B are schematic diagrams of the top and side viewrespectively of the patterned wiring layer of the thin-film circuitlayer with a passive device.

[0025]FIG. 10A is a schematic diagram of the formation of a passivedevice by a single layer of patterned wiring layer of the thin-filmcircuit layer.

[0026]FIG. 10B is a schematic diagram of the formation of a passivedevice by a double layer of patterned wiring layer of the thin-filmcircuit layer.

[0027]FIG. 11A is a schematic diagram of the formation of a passivedevice by a single layer of patterned wiring layer of the thin-filmcircuit layer.

[0028]FIG. 11B is a schematic diagram of the formation of a passivedevice by a double layer of patterned wiring layer of the thin-filmcircuit layer.

[0029]FIG. 11C is a schematic diagram of the formation of a passivedevice by a double layer of patterned wiring layer of the thin-filmcircuit layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Please refer to FIG. 1A, a n organic substrate 110 with a surface112 is provided. The material of the organic substrate comprises polymerresin, epoxy resin, imide resin, or the like, plastic, or thermosettingplastic. The fabrication of the organic substrates can be accomplishedby existing printed circuit board (PCB) fabrication technique. Themethod includes heat pressing a plurality of insulating core boards orinjection molding to form organic substrate 110.

[0031] A plurality of dies 120 having an active surface 122 and acorresponding backside 124 is provided, where the active devices areformed on active surface 122 of dies 120. Furthermore, dies 120 have aplurality of metal pads 126 located on active surface 122 of dies 120acting as the output terminal of dies 120 to transmit signals to theexternal circuitry. Backside 124 of dies 120 is adhered to surface 112of organic substrate 110 by a conductive paste or adhesive tape.Therefore, active surface 122 of dies 120 is facing upwards alongsurface 112 of organic substrate 110.

[0032] Please refer to FIG. 1B, when adhering die 120 to organicsubstrate 110, a filling layer 130 is formed on top of surface 112 oforganic substrate 110 surrounding the peripheral of dies 120 to fill thegap between dies 120. Wherein the top face of filling layer 130 isapproximately planar to active surface 122 of dies 120. The material offilling layer 130 can be epoxy, polymer, or the like. After curing offilling layer 130, a grinding or etching process is applied to planarizefilling layer 130 so the top face of filling layer 130 is planar toactive surface 122 of dies 120.

[0033] Please refer to FIG. 1C, after the formation of filling layer 130on organic substrate 110, a dielectric layer 142 is formed on top offilling layer 130 and active surface 122 of dies 120. Dielectric layer142 is patterned according to metal pads 126 on dies 120 to formthru-holes 142 a. The material of dielectric layer 142 can be poly-Imide(PI), benzocyclobutene (BCB), porous dielectric material, stress buffermaterial, or the like. Patternization of dielectric layer 142 can beperformed by photo via, laser ablation, plasma etching, or the like.

[0034] Please continue to refer to FIG. 1C, filling layer 130 is used tosupport dielectric layer 142 so dielectric layer 142 can be formedplanarized on top of organic substrate 110 and dies 120 without anuneven surface. As a result, after dielectric layer 142 is formed onsurface 112 of organic substrate 110 and active surface 122 of dies 120,dielectric layer 142 also fills the peripheral of dies 120, meaning thegap between dies 120. Therefore the bottom structure of dielectric layer142 can replace the structure of filling layer 130 covering entirelysurface 112 of organic substrate 110 and surrounding dies 120. Themethod of forming dielectric layer 142 includes first depositing a layerof dielectric layer 142 entirely over dies 120 and organic substrate110, then after curing, grinding or etching process is performed toplanarize dielectric layer 142.

[0035] Please refer to FIG. 1D, after forming dielectric layer 142 andpatterning dielectric layer 142 to form thru-holes 142 a, a patternedwiring layer 144 is formed on top of dielectric layer 142 byphotolithography and sputtering, electroplating, or electro-lessplating. Wherein part of the conductive material from patterned wiringlayer 144 will be injected into thru-holes 142 a to form vias 142 b,copper (Cu) is used as the material for patterned wiring layer 144.Moreover, thru-holes 142 a can be pre-filled with a conductive materialsuch as a conductive glue to form vias 142 b. Therefore no matter if thethru-holes are filled with the conductive material from patterned wiringlayer 144 or pre-filled with a conductive material, patterned wiringlayer 144 is electrically connected to metal pads 126 of dies 120. It isto be noted that part of patterned wiring layer 144 extends to a regionoutside active surface 122 of dies 120. Dielectric layer 142 andpatterned wiring layer 144 form a thin-film circuit layer 140.

[0036] Please refer to FIG. 1E, after the formation of patterned wiringlayer 144, another dielectric layer 146 can be formed similarly todielectric layer 142 on top of dielectric layer 142 and patterned wiringlayer 144. Dielectric layer 146 is also patterned to form thru-holes 146a, whereas thru-holes 146 a correspond to bonding pads 144 a ofpatterned wiring layer 144.

[0037] Please refer to FIG. 1F, after the formation and patternizationof dielectric layer 146 to form thru-holes 146 a, a patterned wiringlayer 148 can be formed on dielectric layer 146 in a similar way aspatterned wiring layer 144. Wherein part of the conductive material frompatterned wiring layer 148 will be injected into each thru-hole 146 afor forming a via 146 b. By the same token, patterned wiring layer 148is electrically connected to patterned wiring layer 144 by vias 146 b,and further electrically connected to metal pads 126 of die 120 by vias142 b of thru-hole 142 a. Therefore, thin-film circuit layer 140 furthercomprises dielectric layer 146, a plurality of vias 146 b, and patternedwiring layer 148.

[0038] Please continue to refer to FIG. 1F, in order to redistribute allmetal pads 126 of dies 120 on organic substrate 110, the number ofpatterned wiring layers (144, 148 . . . ) and dielectric layers (142,146 . . . ) for electrical insulation may be increased. All patternedwiring layers (144, 148 . . . ) are electrically connected by vias (146b . . . ) of thru-holes (146 a . . . ). However if only the firstpatterned wiring layer 144 is required to entirely redistribute metalpads 126 of dies 120 on organic substrate 110, extra dielectric layers(146 . . . ) and patterned wiring layers (148 . . . ) will no longer berequired in the structure. In other words, thin-film circuit layer 140comprises at least one dielectric layer 142, one patterned wiring layer144, and a plurality of vias 142 b. Wherein patterned wiring layer (144,148 . . . ) and vias (142 b, 146 b . . . ) of thin-film circuit layer140 form an external circuitry of thin-film circuit layer 140.

[0039] Please refer to FIG. 1G, after the formation of patterned wiringlayer 148, a patterned passivation layer 150 is formed on top ofdielectric layer 146 and patterned wiring layer 148. Patternedpassivation layer 150 is used to protect patterned wiring layer 148 andexpose the plurality of bonding pads 148 a of patterned wiring layer148, whereas some of bonding pads 148 a are in a region outside activesurface 122 of dies 120. As previously mentioned, the redistribution ofmetal pads 126 on organic substrate 110 requires multiple layers ofpatterned wiring layers (144, 148 . . . ) and a patterned passivationlayer 150 formed on the very top, which is furthest away from organicsubstrate 110. However, if only patterned wiring layer 144 is requiredto redistribute all metal pads 126 of dies 120 on organic substrate 110,patterned passivation layer 150 will be formed directly on patternedwiring layer 144. The material of patterned passivation layer 150 can beanti-solder insulating coating or other insulating material.

[0040] Please refer to FIG. 1H, after the formation of patternedpassivation layer 150, a bonding point 160 can be placed on bonding pads148 a serving as an interface for electrically connecting dies 120 tothe external circuitry. Wherein bonding point 160 illustrated in FIG. 1His a ball but it is not limited to any formation, which might include abump, pin, or the like. Wherein ball connector maybe solder ball, andbump connector maybe solder bump, gold bump, or the like.

[0041] Please refer to FIG. 1I, after the formation of bonding points160 on bonding pads 148 a, a singularization process of packaged die 120by mechanical or laser cutting is performed along the dotted line asindicated in the diagram. Afterwards, the chip package structure of thedie is completed.

[0042] According to the above, the first embodiment of the presentinvention is a chip package structure with an organic substrate and aplurality of dies on the organic substrate. The external circuitry ofthe thin-film circuit layer allows the metal pads of the die to fan out.By forming bonding pads corresponding to the metal pads of the dies suchas solders balls, bumps, or pins as the signal input terminals, thedistance of the signal path is effectively decreased. As a result,signal delay and attenuation are reduced to increase performance of thedie.

[0043] The present invention uses existing technology on and equipmentfor fabricating PCB for the fabrication of the organic substrate by heatpressing a plurality of insulating core boards. Alternatively, theorganic substrate can also be fabricated in large volume by injectionmolding. As a result of the low fabrication and material cost of theorganic substrate, the cost of chip packaging is also lowered.

[0044] The second embodiment of the present invention differs from thefirst embodiment by having inwardly protruded areas in the organicsubstrate. This area is for placement of the die with the backside ofthe die adhered to the bottom of the area so the overall thickness ofthe chip package structure is reduced. FIGS. 2A to 2C are schematicdiagrams of the sectional view of the second embodiment illustrating thefabrication of the structure.

[0045] Please refer to FIG. 2A, an organic substrate 210 with a surface212 is provided. In FIG. 2B, a plurality of inwardly protruded areas 214is formed on surface 212 of organic substrate 210 by machining such asmilling. The depth of each inwardly protruded area 214 is approximatelyequal to the thickness of die 220, therefore the outline and depth ofinwardly protruded areas 214 will be the same as dies 220 in FIG. 2C. InFIG. 2C, backside 224 of dies 220 is adhered to the bottom of inwardlyprotruded areas 214 so dies 220 are inlayed in inwardly protruded areas214. Active surface 222 of dies 220 is exposed along surface 212 oforganic substrate 210.

[0046] An alternative method of forming inwardly protruded areas 214 inorganic substrate 210 in FIG. 2B is applying the existing technique isfabricating PCB on two core boards: a first organic layer 210 a and asecond organic layer 210 b, as illustrated in FIG. 2D. Organic layer 210a has openings 214 a and by overlapping the first organic layer 210 aand the second organic layer 210 b and heat pressing them together,openings 214 a in organic layer 210 a will form inwardly protruded areas214 in organic layer 210 b as seen before in FIG. 2B, as illustrated inFIG. 2E. The thickness of organic layer 210 a is approximately equal tothat of die 220 so the depth of inwardly protruded areas 214 isapproximately equal to the thickness of die 220.

[0047] The structure of the second embodiment of the present inventionafter FIG. 2C will follow FIGS. 1C to 1I from the first embodiment ofthe present invention, therefore it will not be repeated.

[0048] The second embodiment of the present invention is an organicsubstrate with a plurality of inwardly protruded areas for inlaying diesby adhering the backside of the dies to the bottom of the inwardlyprotruded areas and exposing the active surface of the dies. A thin-filmcircuit layer is formed on top of the dies and the organic substrate tofan out the metal pads of the dies by using the external circuitry ofthe thin-film circuit layer. Due to the inlay of the dies in the organicsubstrate, thinning of the thickness of the chip package structure iseffectively achieved and the surface of the organic substrate providesenough planarity and support for the formation of the thin-film circuitlayer.

[0049] The third embodiment of the present invention differs from thesecond embodiment of the present invention by using an integratedorganic substrate with at least one organic layer and one heatconducting layer. FIGS. 3A to 3C are schematic diagrams of the sectionalview of the third embodiment illustrating the fabrication of thestructure.

[0050] Please refer to FIG. 3A, an integrated organic substrate 310consists of an organic layer 310 a with multiple openings 314 a and aheat conducting layer 310 b, wherein the material of heat conductinglayer 310 b maybe metal. In FIG. 3B, organic layer 310 a is placedoverlapping heat conducting layer 310 b so openings 314 a of organiclayer 310 a form inwardly protruded areas 314 on heat conducting layer310 b. Following in FIG. 3C, backside 324 of die 320 is adhered to thebottom of inwardly protruded areas 314 so dies 320 are inlayed inorganic substrate 310 with active surface 322 of die 320 exposed alongsurface 312 of organic board 310.

[0051] The following presents two ways of forming integrated organicsubstrate 310 with inwardly protruded areas 314 as shown in FIG. 3B. InFIG. 3A, organic layer 310 a with openings 314 a is provided, openings314 a are formed at the same time when organic layer 310 a is formed forexample by injection molding. In FIG. 3B, organic layer 310 a isoverlapped on heat conducting layer 310 b so openings 314 a of organiclayer 310 a can form inwardly protruded areas 314 on the surface of heatconducting layer 310 b.

[0052] The structure of the third embodiment of the present inventionafter FIG. 3C will follow FIGS. 1C to 1I from the first embodiment ofthe present invention, therefore it will not be repeated.

[0053] The third embodiment of the present invention is an integratedorganic substrate with an organic layer with a plurality of openings anda heat conducting layer. The openings in the organic layer will form theinwardly protruded areas in the integrated organic substrate. Thebackside of the die adheres to the bottom of the inwardly protrudedareas so the dies are inlayed in the inwardly protruded areas andexposing the active surface of the dies. This integrated organicsubstrate can efficiently dissipate heat from the dies to the outsidebecause the bottom of the inwardly protruded area is the surface of theheat conducting material. The surface of the organic substrate providesenough planarity and support for the formation of the thin-film circuitlayer.

[0054] The fourth embodiment of the present invention is slightlydifferent from the first three embodiments. FIGS. 4A to 4E are schematicdiagrams of the sectional view of the fourth embodiment illustrating thefabrication of the structure.

[0055] Please refer to FIG. 4A, an organic substrate 410 with a firstsurface 412 and a plurality of dies 420 are provided. The dies 420 havean active surface 422, a backside 424, and a plurality of metal pads 426located on active surface 422. The fourth embodiment of the presentinvention differs from the third embodiment of the present invention byplacing active surface 422 of die 420 downwards facing first surface 412of organic substrate 410.

[0056] Please refer to FIG. 4B, a filling layer 430 is formed on top offirst surface 412 of organic substrate 410 after active surface 422 ofdie 420 is adhered to first surface 412 of organic substrate 410.Filling layer 430 covers entirely first surface 412 of organic substrate410 and surrounds dies 420. The material of filling layer 430 maybe anoxide, epoxy, or the like.

[0057] Please refer to FIG. 4C, after the formation of filling layer430, a planarization process such as grinding is performed to planarizefilling layer 430 and backside 424 of dies 420. Although the thicknessof the active devices and traces (not shown) on active surface 422 ofdie 420 is much less than that of die 420, the thickness of die 420should not be too small because cracks or damage to the die will occurduring machine handling. However the present invention directly adheresactive surface 422 of dies 420 to first surface 412 of organic substrate410 without further machine handling. Afterwards a grinding process isperformed on backside 424 of dies 420 to reduce the thickness of dies420. As a result, dies 420 are ground to a very small thickness allowingthe final chip package structure to be much thinner.

[0058] Please refer to FIG. 4D, after the planarization of filling layer430 and dies 420, a second organic substrate 440 with a second surface442 is adhered to filling layer 430 and dies 420 creating a sandwicheffect with filling layer 430 and dies 420 in between two organicsubstrates 410 and 440.

[0059] Please refer to FIG. 4E, after the adhesion of second organicsubstrate 440, a grinding or the like process is performed to thin thebackside of organic substrate 410 to achieve a thickness of about 2microns to 200 microns, usually about 20 microns. First organicsubstrate 410 is used to provide a planar surface for dies 420 to adhereto and to serve as an insulating layer. Therefore organic substrate 410can be replaced by substrate made of glass or other organic material.

[0060] Please refer to FIG. 4F, after the thinning of first organicsubstrate 410, a plurality of first thru-holes 410 a are formed on firstorganic substrate 410 for exposing metal pads 426 on active surface 422of die 420. First thru-holes 410 a can be formed by machine drilling,laser, plasma etching, or similar methods.

[0061] Please refer to FIG. 4G, a first patterned wiring layer 450 isformed on first organic substrate 410. Using the same method disclosedin the first embodiment of the present invention, first vias 410 b infirst thru-holes 410 a are formed by either filling first thru-holes 410a with part of the conductive material from patterned wiring layer 450or pre-filling first thru-holes 410 a with a conductive material beforethe formation of patterned wiring layer 450. A part of patterned wiringlayer 450 will extend to a region outside active surface 422 of die 420.

[0062] Please refer to FIG. 4H, a dielectric layer 462 is formed onfirst organic substrate 410 and first patterned wiring layer 450.Wherein dielectric layer 462 is patterned to form a plurality of secondthru-holes 462 a, which correspond to bonding pad 450 a of patternedwiring layer 450.

[0063] Please refer to FIG. 4I, a second patterned wiring layer 464 isformed on top of dielectric layer 462. Using the same method as above,second vias 462 b in thru-holes 462 a can be formed by either fillingsecond thru-holes 462 a with part of the conductive material frompatterned wiring layer or pre-filling second thru-holes 462 a with aconductive material before the formation of patterned wiring layer 464.Similarly, in order to redistribute metal pads 426 of dies 420 on secondorganic substrate 440, dielectric layer (462 . . . ), second vias (462 a. . . ), and second patterned wiring layer (464 . . . ) can berepeatedly formed on dies 420 and organic substrate 440. Wherein firstorganic substrate 410, first patterned wiring layer 450, dielectriclayer 462 . . . , and second patterned wiring layer 464 . . . formthin-film circuit layer 460. First vias 410 b, first patterned wiringlayer 450, second vias 462 b . . . , and second patterned wiring layer464 form the external circuitry of thin-film circuit layer 460.

[0064] The structure of the fourth embodiment of the present inventionafter FIG. 41 will follow FIGS. 1G to 1I from the first embodiment ofthe present invention, therefore it will not be repeated.

[0065] The fourth embodiment of the present invention is an organicsubstrate with the active surface of the dies adhered directly to thesurface of the first organic substrate. A filling layer is formed overthe dies and the organic substrate followed by a planarization andthinning process. Afterwards, a second organic substrate is adhered tothe die and the filling layer. A thinning process of the first organicsubstrate is performed and a plurality of thru-holes filled withconductive material are formed on the first organic substrate. Finally apatterned wiring layer is formed on the first organic substrate allowingthe external circuitry of the thin-film circuit layer to extend to aregion outside the active surface of the die to help fan out the metalpads of the die.

[0066] The advantage of this structure is increased surface stabilityand accuracy because the active surface of the dies are first adhered tothe surface of the first organic substrate. The thickness of the die canbe very small for reducing the overall thickness of the chip packagebecause no machine handling of dies is required.

[0067] The fifth embodiment of the present invention takes the firsthalf of the fabrication process from the fourth embodiment of thepresent invention and combines with the second half of the fabricationprocess from the first embodiment of the present invention. FIGS. 5A to5E are schematic diagrams of the sectional view illustrating thefabrication of the structure.

[0068] Please refer to FIG. 5A, an active surface 522 of dies 520 isadhered to a first surface 512 of a first organic substrate 510. In FIG.5B, a filling layer 530 is formed on top of dies 520 and first organicsubstrate 510 covering dies 520. In FIG. 5C, a planarization andthinning process of dies 520 and filling layer 530 is performed toplanarize backside 524 of dies 520 and filling layer 530. In FIG. 5D, asecond organic substrate 540 is formed on top of dies 520 and fillinglayer 530 so backside 524 of dies 520 adheres to second organicsubstrate 540. By removing filling layer 530 and first organic substrate510, the metal pads on active surface 522 of dies 520 are exposed. Firstorganic substrate 510 is used to supply a planarized surface (firstsurface 512), and will be removed in later stages of the fabricationprocess. Therefore first organic substrate 510 can be replaced bysubstrates of other materials such as glass, metal, silicon, or otherorganic material.

[0069] The structure of the fifth embodiment of the present inventionafter FIG. 5E will follow FIGS. 1B to 1I of the first embodiment of thepresent invention, therefore it will not be repeated.

[0070] The fifth embodiment of the present invention is an organicsubstrate with the active surface of the dies adhered to the surface ofthe first organic substrate for allowing high surface stability andaccuracy. As a result, it eliminates the need of machine handling of thedies to achieve a very small thickness of the die for reducing theoverall thickness of the chip package.

[0071] Furthermore, please refer to FIG. 6, it illustrates the schematicdiagram of the sectional view of the chip package structure 600 of thepresent invention for a single die 620. Die 620 is placed on organicsubstrate 610, and a thin-film circuit layer 640 is formed on top of die620 and organic substrate 610. External circuitry 642 of thin-filmcircuit layer 640 has at least has one patterned wiring layer 642 a anda plurality of vias 642 b. The thickness of the inner traces inside die620 is usually under 1 micron, but because the high amount of tracescollocated together so RC delay is relatively high and the power/groundbus requires a large area. As a result, the area of die 620 is notenough to accommodate the power/ground bus. Therefore the chip packagestructure 600 uses thin-film circuit layer 640 and external circuitry642 with wider, thicker, and longer traces to alleviate the problem.These traces act an interface for transmitting signals for the internalcircuitry of die 620 or the power/ground bus of die 620. This willimprove the performance of die 620.

[0072] Please refer to FIG. 8, it illustrates a magnified view of thesectional view of the chip package structure of the present invention.Active surface 622 of die 620 has a plurality of active devices 628 a,628 b, and an internal circuitry 624. The internal circuitry 624 forms aplurality of metal pads 626 on the surface of die 620. Therefore signalsare transmitted from active devices 628 a to external circuitry 642 viainternal circuitry 624 of die 620, and from external circuitry 642 backto another active device 628 b via internal circuitry 624. The traces ofexternal circuitry 642 are wider, longer, and thicker than that ofinternal circuitry 624 for providing an improved transmission path.

[0073] Please continue to refer to FIG. 6, external circuitry 642further comprises at least one passive device 644 including a capacitor,an inductor, a resistor, a wave-guide, a filter, a micro electronicmechanical sensor (MEMS), or the like. Passive device 644 can be locatedon a single layer of patterned wiring layer 642 a or between two layersof patterned wiring layers 642 a. In FIGS. 9A, 9B, passive device 644can be formed by printing or other method on two bonding points onpatterned wiring layer 642 a when forming thin-film layer 640. In FIG.10A, a comb-shape passive device 644 (such as a comb capacitor) isformed directly on a single patterned wiring layer. In FIG. 10B, passivedevice 644 (such as a capacitor) is formed between two layers ofpatterned wiring layers 642 a with an insulating material 646 inbetween. Wherein the original dielectric layer (not shown) can replaceinsulating material 646. In FIG. 11A, passive device 644 (such as aninductor) is formed by making a single layer of patterned wiring layer642 a into a circular or square (not shown) spiral. In FIG. 11B,column-shape passive device 644 (such as an inductor) is formed by usingtwo layers of patterned wiring layers 642 a and a plurality of vias 642b to surround an insulating material 646 forming a column. In FIG. 11C,circular-shaped passive device 644 (such as an inductor) is formed byusing slanted traces from two layers of patterned wiring layers and aplurality of vias 642 b to surround an insulating material 646 in acircular manner forming a pie. The above structures allow the originalexternally welded passive devices to be integrated into the inside ofthe chip package structure.

[0074]FIG. 6 illustrates a chip package structure 600 for a single die620 but FIG. 7 illustrates a chip package structure 700 for a pluralityof dies. Chip package structure 700 in FIG. 7 differs from chip packagestructure 600 in FIG. 6 by having a die module 720, which comprises atleast one or more dies such as die 720 a, 720 b. Die 720 a, 720 b areelectrically connected by the external circuitry of the thin-filmcircuit layer. The function of die 720 a, 720 b can be the same ordifferent and can be integrated together by external circuitry 742 toform a multi-die module (MCM) by packaging same or different dies intoone chip package structure. When multiple dies are packaged into thesame chip package structure, singulation process is performed on thedetermined number of dies.

[0075] Following the above, the present invention provides a chippackaging method by adhering a die to an organic substrate or to aninwardly protruded area of an organic substrate, and forming a thin-filmcircuit layer with bonding pads and points above the die and organicsubstrate. This structure can fan out the metal pads on the die toachieve a thin chip package structure with high pin count.

[0076] Comparing to the BGA or PGA package technique used in the priorart, the chip package of the present invention is performed directly onthe die and the organic substrate for fanning out the metal pads on thedie. It does not require flip chip or wire bonding to connect the die tothe micro-spaced contact points of a package substrate or carrier. Thepresent invention can reduce cost because the package substrate withmicro-spaced contacts is very expensive. Moreover the signaltransmission path of the present invention is reduced to lessen theeffect of signal delay and attenuation, which improves the performanceof the die.

[0077] Furthermore, the present invention uses organic substrate as thepackage substrate of a chip carrier. The organic substrate can be formedby existing PCB fabrication method such as heating pressing a pluralityof insulating core boards or injection molding for high volumeproduction. The abundance of organic material and existingwell-known-in-the-art technique on fabrication of organic material cangreatly reduce cost of the organic substrate to lower the cost of thechip packaging.

[0078] Furthermore, the third embodiment of the present inventionprovides an integrated substrate comprises an organic layer and a heatconducting layer. A plurality of openings can be pre-formed on theorganic layer so inwardly protruded areas are formed for inlaying thedie when the organic layer overlaps the heat conducting layer. The heatconducting layer helps to dissipate heat to the outside from the dieduring operation, which will effectively increase performance.

[0079] The thin-film layer circuit of the present invention is used totransmit signals between two main active devices inside the die, used asa power/ground bus, or used to add in passive devices. Furthermore, thechip package structure of the present invention can accommodate one ormore dies with similar or different functions. The external circuitry ofthe thin-film circuit layer electrically connects the multiple diestogether and can be used in a MCM package. The chip package structure ofthe present invention adapts the MCM, the external circuitry of thethin-film circuit layer, the passive devices of the external circuitryto form a package that is called “system in package”.

[0080] It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A chip package structure comprising: an organicsubstrate; a die, wherein the die has an active surface, a backside thatis opposite to the active surface, and a plurality of metal pads locatedon the active surface, whereas the backside of the die is adhered to theorganic substrate; and a thin-film circuit layer located on top of theorganic substrate and the die and has an external circuitry, wherein theexternal circuitry is electrically connected to the metal pads of thedie and extends to a region outside the active surface of the die, theexternal circuitry has a plurality of bonding pads located on a surfacelayer of the thin-film circuit layer and each bonding pad iselectrically connected to the corresponding metal pad of the die.
 2. Thestructure in claim 1, wherein the die has an internal circuitry and aplurality of active devices located on the active surface of the die andthe internal circuitry is electrically connected to the active devices,whereas the internal circuitry forms the metal pads.
 3. The structure inclaim 2, wherein a signal from one of the active devices is transmittedto the external circuitry via the internal circuitry, and from theexternal circuitry back to one of the active devices via the internalcircuitry.
 4. The structure in claim 3, wherein a width, length, andthickness of traces of the external circuitry are greater thancorresponding traces of the internal circuitry.
 5. The structure inclaim 1, wherein the external circuitry further comprising apower/ground bus.
 6. The structure in claim 1, wherein the thin-filmcircuit layer comprising at least a patterned wiring layer and adielectric layer, the dielectric layer is located on top of the organicsubstrate and the die, and the patterned wiring layer is located on topof the dielectric layer, whereas the patterned wiring layer iselectrically connected to the metal pads of the die through thedielectric layer and forms the external circuitry and the bonding padsof the external circuitry.
 7. The structure in claim 6, wherein thedielectric layer has a plurality of thru-holes, and the patterned wiringlayer is electrically connected to the metal pads of the die by thethru-holes.
 8. The structure in claim 6, wherein a via is located insideeach thru-hole, and the patterned wiring layer is electrically connectedto the metal pads of the die by the vias.
 9. The structure in claim 6,wherein the patterned wiring layer and the vias form the externalcircuitry.
 10. The structure of the claim 6, wherein the externalcircuitry further comprising at least one passive device.
 11. Thestructure in claim 6, wherein the passive device is selected from agroup consisting of a resistor, an inductor, a capacitor, a wave-guide,a filter, and a micro electronic mechanical sensor (MEMS).
 12. Thestructure in claim 10, wherein the passive device is formed by a part ofthe patterned wiring layer.
 13. The structure in claim 6, wherein amaterial of the dielectric layer is selected from a group consisting ofpolyimide, benzocyclobutene, porous dielectric material, and stressbuffer material.
 14. The structure in claim 1, wherein the thin-filmcircuit layer comprising a plurality of patterned wiring layers and aplurality of dielectric layers, in which the patterned wiring layers anddielectric layers are alternately formed and the patterned wiring layersare electrically connected to the neighboring patterned wiring layersthrough the dielectric layer, one of the dielectric layers is formedbetween the thin-film circuit layer and the organic substrate, thepatterned wiring layer that is closest to the organic substrate iselectrically connected to the metal pads of the die through thedielectric layer that is closest to the organic substrate, where thepatterned wiring layer that is furthest away from the organic substrateforms the bonding pads.
 15. The structure in claim 14, wherein each ofthe dielectric layers has a plurality of thru-holes, by which each ofthe patterned wiring layer is electrically connected the neighboringpatterned wiring layers, where the patterned wiring layer that isclosest to the organic substrate is electrically connected to the metalpads of the die through the dielectric layer.
 16. The structure in claim15, wherein a via is located in each thru-hole, by which the patternedwiring layers are electrically connected to the neighboring patternedwiring layers, where the patterned wiring layer that is closest to theorganic substrate is electrically connected to the metal pads of the dieby the vias.
 17. The structure in claim 16, wherein the patterned wiringlayers and the vias form the external circuitry.
 18. The structure inclaim 14, wherein the external circuitry further comprising a passivedevice.
 19. The structure in claim 18, wherein the passive device isselected from a group consisting of a resistor, an inductor, acapacitor, a wave-guide, a filter, and a micro electronic mechanicalsensor (MEMS).
 20. The structure in claim 18, wherein the passive deviceis formed by a part of the patterned wiring layer.
 21. The structure inclaim 18, wherein a material of the dielectric layer is selected from agroup consisting of polyimide, benzocyclobutene, porous dielectricmaterial, and stress buffer material.
 22. The structure in claim 1,wherein the organic substrate further comprising an inwardly protrudedarea located on a surface of the organic substrate, where the backsideof the die is adhered to a bottom of the inwardly protruded area. 23.The structure in claim 1, wherein the organic substrate comprising anorganic layer and a heat conducting layer formed overlapping, a surfaceof the organic substrate is a side of the heat conducting layer that isfurther away from the organic layer, the organic layer has at least oneopening that penetrates through the organic layer used to form aninwardly protruded area, and the backside of the die is adhered to abottom of the inwardly protruded area.
 24. The structure in claim 23,wherein the heat conducting layer comprising a metal.
 25. The structurein claim 1 further comprising a filling layer located between a surfaceof the organic substrate and the thin-film circuit layer and surroundingthe peripheral of the die, and a surface of the filling layer is planarto the active surface of the die.
 26. The structure in claim 25, whereina material of the filling layer is selected from a group consisting ofepoxy and polymer.
 27. The structure in claim 1 further comprising apassivation layer located on top of the thin-film circuit layer andexposing the bonding pads.
 28. The structure in claim 1 furthercomprising a plurality of bonding points located on the bonding pads.29. The structure in claim 28, wherein the bonding points are selectedfrom a group consisting of solder balls, bumps, and pins.
 30. A chippackage structure comprising: an organic substrate; a plurality of dies,wherein each die has an active surface, a backside that is opposite tothe active surface, and a plurality of metal pads located on the activesurface, whereas the backside of each die is adhered to the organicsubstrate; and a thin-film circuit layer located on top of the organicsubstrate and the die and has an external circuitry, wherein theexternal circuitry is electrically connected to the metal pads of thedie and extends to a region outside the active surface of the die, theexternal circuitry has a plurality of bonding pads located on a surfacelayer of the thin-film circuit layer and each bonding pad iselectrically connected to a corresponding metal pad of the die.
 31. Thestructure in claim 30, wherein the dies perform same functions.
 32. Thestructure in claim 30, wherein the dies perform different functions. 33.The structure in claim 30, wherein the dies have an internal circuitryand a plurality of active devices located on the active surface of thedie, and the internal circuitry is electrically connected to the activedevices, whereas the internal circuitry forms the metal pads.
 34. Thestructure in claim 33, wherein a signal from one of the active devicesis transmitted to the external circuitry via the internal circuitry, andfrom the external circuitry back to one of the active devices via theinternal circuitry.
 35. The structure in claim 34, wherein a width,length, and thickness of the traces of the external circuitry aregreater than corresponding traces of the internal circuitry.
 36. Thestructure in claim 30, wherein the external circuitry further comprisinga power/ground bus.
 37. The structure in claim 30, wherein the thin-filmcircuit layer comprising at least a patterned wiring layer and adielectric layer, the dielectric layer is located on top of the organicsubstrate and the die, and the patterned wiring layer is located on topof the dielectric layer, whereas the patterned wiring layer iselectrically connected to the metal pads of the die through thedielectric layer and forms the external circuitry and the bonding padsof the external circuitry.
 38. The structure in claim 37, wherein thedielectric layer has a plurality of thru-holes, and the patterned wiringlayer is electrically connected to the metal pads of the die by thethru-holes.
 39. The structure in claim 38, wherein a via is locatedinside each thru-hole, and the patterned wiring layer is electricallyconnected to the metal pads of the die by the vias.
 40. The structure inclaim 39, wherein the patterned wiring layer and the vias form theexternal circuitry.
 41. The structure of the claim 37, wherein theexternal circuitry further comprising at least one passive device. 42.The structure in claim 41, wherein the passive device is selected from agroup consisting of a resistor, an inductor, a capacitor, a wave-guide,a filter, and a micro electronic mechanical sensor (MEMS).
 43. Thestructure in claim 41, wherein the passive device is formed by a part ofthe patterned wiring layer.
 44. The structure in claim 37, wherein amaterial of the dielectric layer is selected from a group consisting ofpolyimide, benzocyclobutene, porous dielectric material, and stressbuffer material.
 45. The structure in claim 30, wherein the thin-filmcircuit layer comprising a plurality of patterned wiring layers and aplurality of dielectric layers, in which the patterned wiring layers anddielectric layers are alternately formed and the patterned wiring layersare electrically connected to the neighboring patterned wiring layersthrough the dielectric layer, one of the dielectric layers is formedbetween the thin-film circuit layer and the organic substrate, thepatterned wiring layer that is closest to the organic substrate iselectrically connected to the metal pads of the dies through thedielectric layer that is closest to the organic substrate, where thepatterned wiring layer that is furthest away from the organic substrateforms the bonding pads.
 46. The structure in claim 45, wherein each ofthe dielectric layers has a plurality of thru-holes, by which each ofthe patterned wiring layer is electrically connected the neighboringpatterned wiring layers, where the patterned wiring layer that isclosest to the organic substrate is electrically connected to the metalpads of the dies through the dielectric layer.
 47. The structure inclaim 46, wherein a via is located in each thru-hole, by which thepatterned wiring layers are electrically connected to the neighboringpatterned wiring layers, where the patterned wiring layer that isclosest to the organic substrate is electrically connected to the metalpads of the die by the vias.
 48. The structure in claim 47, wherein thepatterned wiring layers and the vias form the external circuitry. 49.The structure in claim 45, wherein the external circuitry furthercomprising a passive device.
 50. The structure in claim 49, wherein thepassive device is selected from a group consisting of a resistor, aninductor, a capacitor, a wave-guide, a filter, and a micro electronicmechanical sensor (MEMS).
 51. The structure in claim 49, wherein thepassive device is formed by a part of the patterned wiring layer. 52.The structure in claim 45, wherein a material of the dielectric layer isselected from a group consisting of polyimide, benzocyclobutene, porousdielectric material, and stress buffer material.
 53. The structure inclaim 30, wherein the organic substrate further comprising a pluralityof inwardly protruded areas located on a surface of the organicsubstrate and the backside of the dies is adhered to a bottom of theinwardly protruded areas.
 54. The structure in claim 30, wherein theorganic substrate comprising an organic layer and a heat conductinglayer formed thereon together, a top surface of the organic substrate isa side of the heat conducting layer that is further away from theorganic layer, the organic layer has a plurality of openings thatpenetrate through the organic layer used to form the inwardly protrudedareas, and the backside of the dies are adhered to a bottom of theinwardly protruded areas.
 55. The structure in claim 54, wherein theheat conducting layer comprising a metal.
 56. The structure in claim 30farther comprising a filling layer located between a surface of theorganic substrate and the thin-film circuit layer and surrounding theperipheral of the die, and a surface of the filling layer is planar tothe active surface of the die.
 57. The structure in claim 56, wherein amaterial of the filling layer is selected from a group consisting ofepoxy and polymer.
 58. The structure in claim 30 further comprising apassivation layer located on top of the thin-film circuit layer andexposing the bonding pads.
 59. The structure in claim 30 furthercomprising a plurality of bonding points located on the bonding pads.60. The structure in claim 59, wherein the bonding points are selectedfrom a group consisting of solder balls, bumps, and pins.
 61. A chippackaging method comprising: providing an organic substrate with asurface; providing a plurality of dies, wherein each die has an activesurface, a backside that is opposite to the active surface, and aplurality of metal pads located on the active surface, whereas thebackside of each die is adhered to the surface of the organic substrate;allocating a first dielectric layer on top of the surface of the organicsubstrate and the active surface of the dies; and allocating a firstpatterned wiring layer on top of the first dielectric layer, wherein thefirst patterned wiring layer is electrically connected to the metal padsof the dies through the first dielectric layer, extends to a regionoutside of an area above the active surfaces of the dies, and has aplurality of first bonding pads.
 62. The method of claim 61, wherein thedies perform same functions.
 63. The method of claim 61, wherein thedies perform different functions.
 64. The method of claim 61, whereinthe organic substrate has a plurality of inwardly protruded areaslocated on the surface of the organic substrate, where the backside ofeach die is adhered to a bottom of an inwardly protruded area.
 65. Themethod of claim 64, wherein the organic substrate comprising at least afirst insulating core board and a second insulating core board formedoverlapping, wherein the first insulating core board has a plurality ofopenings used to form inwardly protruded areas with the secondinsulating core board.
 66. The method of claim 64, wherein the openingsand the organic substrate are formed together and a method offabricating the organic substrate comprising injection molding.
 67. Themethod of claim 64, wherein the organic substrate comprising an organiclayer and a heat conducting layer formed overlapping, a surface of theorganic substrate is a side of the heat conducting layer that is furtheraway from the organic layer, the organic layer has a plurality ofopenings that penetrates through the organic layer used to form theinwardly protruded areas, and the backside of the dies is adhered to abottom of the inwardly protruded areas.
 68. The method of claim 67,wherein the openings and the organic substrate are formed together and amethod of fabricating the organic substrate comprising injectionmolding.
 69. The method of claim 67, wherein the heat conducting layercomprising a metal.
 70. The method of claim 61, wherein after adheringthe dies and before allocating the first dielectric layer, furthercomprising allocating a filling layer on top of the surface of theorganic substrate and surrounding the peripheral of the dies, and a topsurface of the filling layer is planar to the active surface of thedies.
 71. The method of claim 70, wherein a material of the fillinglayer is selected from a group consisting of epoxy and polymer.
 72. Themethod of claim 61, wherein after allocating the first dielectric layerand before allocating the first patterned wiring layer, furthercomprising patterning the first dielectric layer to form a plurality offirst thru-holes that penetrates through the first dielectric layer, andthe first patterned conductive is electrically connected to the metalpads of the dies by the first thru-holes.
 73. The method of claim 72,wherein when allocating the first patterned wiring layer on the firstdielectric layer, further includes allocating a plurality of first viasby filling part of a conductive material of the first patternedconductive layer into the first thru-holes to electrically connect thefirst patterned wiring layer and the metal pads of the dies by the firstvias.
 74. The method of claim 72, wherein when allocating the firstpatterned wiring layer on top of the first dielectric layer, furthercomprising filling the first thru-holes with a conductive material toform a plurality of first vias, by which the first patterned wiringlayer and the metal pads are electrically connected.
 75. The method ofclaim 61, wherein a material of the first dielectric layer is selectedfrom a group consisting of polyimide, benzocyclobutene, porousdielectric material, and stress buffer material.
 76. The method of claim61, wherein the method of allocating the first patterned wiring layer ontop of the first dielectric layer is selected from a group consisting ofsputtering, electroplating, and electro-less plating.
 77. The method ofclaim 61, further comprising allocating a patterned passivation layer ontop of the first dielectric layer and the first patterned wiring layerand exposing the first bonding pads.
 78. The method of claim 61, furthercomprising allocating a bonding point on the first bonding pads.
 79. Themethod of claim 78, wherein the bonding points are selected from a groupconsisting of solder balls, bumps, and pins.
 80. The method of claim 78,further comprising singularizing the chip package structure afterallocating the bonding point on the bonding pads.
 81. The method ofclaim 80, wherein a singularization of the chip package structure isperformed on a single die.
 82. The method of claim 80, wherein asingularization of the chip package structure is performed on aplurality of dies.
 83. The method of claim 61 further comprising: (a)allocating a second dielectric layer on top of the first dielectriclayer and the first patterned wiring layer; and (b) allocating a secondpatterned wiring layer on top the second dielectric layer, wherein thesecond patterned wiring layer is electrically connected to the firstpatterned wiring layer through the second dielectric layer, and thesecond patterned wiring layer extends to a region outside the activesurface of the die and has a plurality of second bonding pads.
 84. Themethod of claim 83, wherein after allocating the second dielectric layerand before allocating the second patterned wiring layer, furthercomprising patterning the second dielectric layer to form a plurality ofsecond thru-holes, which corresponds to the first thru-holes andpenetrates the second dielectric layer, to electrically connect to thefirst patterned wiring layer.
 85. The method of claim 84, wherein whenallocating the second patterned wiring layer on top of the seconddielectric layer, further comprising filling the second thru-holes withpart of a conductive material of the second patterned wiring layer toform a plurality of second vias, by which the second patterned wiringlayer is electrically connected to the first patterned wiring layer. 86.The method of claim 84, wherein before allocating the second patternedwiring layer on top of the second dielectric layer, further comprisingfilling the second thru-holes with a conductive material to form aplurality of second vias, by which the second patterned wiring layer iselectrically connected to the first patterned wiring layer.
 87. Themethod of claim 83, wherein a material of the second dielectric layer isselected from a group consisting of polyimide, benzocyclobutene, porousdielectric material, and stress buffer material.
 88. The method of claim83, wherein the method of allocating the second patterned wiring layeron the second dielectric layer is selected from a group consisting ofsputtering, electroplating, and electro-less plating.
 89. The method ofclaim 83, further comprising allocating a patterned passivation layer ontop of the second dielectric layer and the second patterned wiring layerand exposing the second bonding pads.
 90. The method of claim 83,further comprising allocating a bonding point on the second bondingpads.
 91. The method of claim 90, wherein the bonding points areselected from a group consisting of solder balls, bumps, and pins. 92.The method of claim 90, further comprising singularizing the chippackage structure after allocating the bonding point on the secondbonding pads.
 93. The method of claim 92, wherein a singularization ofthe chip package structure is performed on a single die.
 94. The methodof claim 92, wherein a singularization of the chip package structure isperformed on a plurality of dies.
 95. The method of claim 83, furthercomprising repeating step (a) and step (b) a plurality of times.
 96. Themethod of claim 95 further comprising allocating a patterned passivationlayer on the second dielectric layer and the second patterned wiringlayer that is furthest away from the organic substrate and exposing thesecond bonding pads of the second patterned wiring layer that isfurthest away from the organic substrate.
 97. The method of claim 95,further comprising allocating a bonding point on the second bonding padsof the second dielectric layer that is furthest away from the organicsubstrate.
 98. The method of claim 97, wherein the bonding points areselected from a group consisting of solder balls, bumps, and pins. 99.The method of claim 97, further comprising singularizing the chippackage structure after allocating the bonding point on the secondbonding pads.
 100. The method of claim 99, wherein a singularization ofthe chip package structure is performed on a single die.
 101. The methodof claim 100, wherein a singularization of the chip package structure isperformed on a plurality of dies.
 102. A chip packaging methodcomprising: providing an insulating substrate with a first surface;providing a plurality of dies, wherein each die has an active surfaceand a backside that is opposite to the active surface and a plurality ofmetal pads located on the active surface, whereas the active surface ofeach die is adhered to the first surface of the insulating substrate;allocating a filling layer on top of the first surface of the insulatingsubstrate and surrounding the dies; planarizing and thinning of thefilling layer and the dies; providing an organic substrate with a secondsurface and adhering the second surface of the organic substrate to thefilling layer and the dies; and allocating a first patterned wiringlayer on top of the insulating substrate, wherein the first patternedwiring layer is electrically connected to the metal pads of the diesthrough the insulating substrate, extends to a region outside the activesurfaces of the dies, and has a plurality of first bonding pads. 103.The method of claim 102, wherein the dies perform same functions. 104.The method of claim 102, wherein the dies perform different functions.105. The method of claim 102, wherein a material of the insulatingsubstrate is selected from a group consisting of glass, organic, andorganic material.
 106. The method of claim 102, wherein a material ofthe filling layer is selected from a group consisting of epoxy andpolymer.
 107. The method of claim 102, wherein a thickness of theinsulating substrate is in a range from about 2 microns to 200 microns.108. The method of claim 102, wherein after adhering the organicsubstrate and before patterning the insulating substrate, furthercomprising thinning a thickness of the insulating substrate.
 109. Themethod of claim 108, wherein a thickness of the insulating substrateafter thinning is in a range from about 2 microns to 200 microns. 110.The method of claim 102, wherein the method of allocating the firstpatterned wiring layer on the insulating substrate is selected from agroup consisting of sputtering, electroplating, and electro-lessplating.
 111. The method of claim 102, wherein before allocating thefirst patterned wiring layer on the insulating substrate, furthercomprising removing part of the insulating substrate to form a pluralityof first thru-holes, the first patterned wiring layer, and a pluralityof first vias, which correspond to the metal pads and penetrate theinsulating substrate, and the first patterned wiring layer iselectrically connected to the metal pads by the first vias.
 112. Themethod of claim 111, wherein when allocating the first patterned wiringlayer on the insulating substrate, further comprising filling the firstthru-holes with part of a conductive material of the first patternedwiring layer to form a plurality of first vias, by which the firstpatterned wiring layer is electrically connected to the metal pads ofthe dies.
 113. The method of claim 111, wherein before allocating thefirst patterned wiring layer on the insulating substrate, furthercomprising filling a conductive material in the first thru-holes to forma plurality of first vias, by which the first patterned wiring layer iselectrically connected to the metal pads of the dies.
 114. The method ofclaim 102 further comprising allocating a patterned passivation layer onthe insulating substrate and the first patterned wiring layer andexposing the first bonding pads.
 115. The method of claim 109 furthercomprising allocating a bonding point on the first bonding pads. 116.The method of claim 115, wherein the bonding points are selected from agroup consisting of solder balls, bumps, and pins.
 117. The method ofclaim 115, further comprising singularizing the chip package structureafter allocating the bonding point on the bonding pads.
 118. The methodof claim 117, wherein a singularization of the chip package structure isperformed on a single die.
 119. The method of claim 117, wherein asingularization of the chip package structure is performed on aplurality of dies.
 120. The method of claim 102 further comprising: (a)allocating a dielectric layer on top of the insulating substrate and thefirst patterned wiring layer; and (b) allocating a second patternedwiring layer on top the insulating substrate, wherein the secondpatterned wiring layer is electrically connected to the first patternedwiring layer through the insulating substrate, and the second patternedwiring layer extends to a region outside of the active surface of thedie and has a plurality of second bonding pads.
 121. The method of claim120, wherein after allocating the dielectric layer and before allocatingthe second patterned wiring layer, further comprising patterning thedielectric layer to form a plurality of second thru-holes, whichcorresponds to the first bonding pads and penetrates the dielectriclayer, to electrically connect to the first patterned wiring layer tothe second patterned wiring layer.
 122. The method of claim 121, whereinwhen allocating the second patterned wiring layer on top of thedielectric layer, further comprising filling the second thru-holes withpart of a conductive material of the second patterned wiring layer toform a plurality of second vias, by which the second patterned wiringlayer is electrically connected to the first patterned wiring layer.123. The method of claim 121, wherein before allocating the secondpatterned wiring layer on top of the dielectric layer, furthercomprising filling the second thru-holes with a conductive material toform a plurality of second vias, by which the second patterned wiringlayer is electrically connected to the first patterned wiring layer.124. The method of claim 120, wherein a material of the seconddielectric layer is selected from a group consisting of polyimide,benzocyclobutene, porous dielectric material, and stress buffermaterial.
 125. The method of claim 120, wherein a method of allocatingthe second patterned wiring layer on the second dielectric layer isselected from a group consisting of sputtering, electroplating, andelectro-less plating.
 126. The method of claim 120, further comprisingallocating a patterned passivation layer on top of the second dielectriclayer and the second patterned wiring layer and exposing the secondbonding pads.
 127. The method of claim 120, further comprisingallocating a bonding point on the second bonding pads.
 128. The methodof claim 127, wherein the bonding points are selected from a groupconsisting of solder balls, bumps, and pins.
 129. The method of claim127, farther comprising singularizing the chip package structure afterallocating the bonding point on the second bonding pads.
 130. The methodof claim 129, wherein a singularization of the chip package structure isperformed on a single die.
 131. The method of claim 129, wherein asingularization of the chip package structure is performed on aplurality of dies.
 132. The method of claim 120, further comprisingrepeating step (a) and step (b) a plurality of times.
 133. The method ofclaim 132 farther comprising allocating a patterned passivation layer onthe second dielectric layer and the second patterned wiring layer thatis furthest away from the organic substrate and exposing the secondbonding pads of the second patterned wiring layer that is furthest awayfrom the organic substrate.
 134. The method of claim 132, furthercomprising allocating a bonding point on the second bonding pads of thesecond patterned wiring layer that are furthest away from the organicsubstrate.
 135. The method of claim 134, wherein the bonding points areselected from a group consisting of solder balls, bumps, and pins. 136.The method of claim 134, further comprising singularizing the chippackage structure after allocating the bonding point on the secondbonding pads.
 137. The method of claim 136, wherein a singularization ofthe chip package structure is performed on a single die.
 138. The methodof claim 136, wherein a singularization of the chip package structure isperformed on a plurality of dies.
 139. A chip packaging methodcomprising: providing a substrate with a first surface; providing aplurality of dies, wherein each die has an active surface, a backsidethat is opposite to the active surface, and a plurality of metal padslocated on the active surface, whereas the active surface of each die isadhered to the first surface of the substrate; allocating a firstfilling layer on top of the first surface of the substrate andsurrounding the dies; planarizing and thinning of the filling layer andthe dies; providing an organic substrate with a second surface andadhering the second surface of the organic substrate to the fillinglayer and the dies; removing the first filling layer and the substrate;allocating a first dielectric layer on the second surface of the organicsubstrate and the active surface of the dies; and allocating a firstpatterned wiring layer on top of the first dielectric layer, wherein thefirst patterned wiring layer is electrically connected to the metal padsof the dies through the first dielectric layer, extends to a regionoutside the active surfaces of the dies, and has a plurality of firstbonding pads.
 140. The method of claim 139, wherein the dies performsame functions.
 141. The method of claim 139, wherein the dies performdifferent functions.
 142. The method of claim 139, wherein a material ofthe substrate is selected from a group consisting of glass, organic, andorganic material.
 143. The method of claim 139, wherein a material ofthe first filling layer is selected from a group consisting of epoxy andpolymer.
 144. The method of claim 139, wherein after adhering theorganic substrate and before removing the first filling layer and thesubstrate, further comprising allocating a second filling layer on topof the second surface of the organic substrate, the second filling layersurrounds a peripheral of the dies and has a top surface that is planarto the active surface of the dies.
 145. The method of claim 144, whereina material of the second filling layer is selected from a groupconsisting of epoxy and polymer.
 146. The method of claim 139, whereinafter allocating the first dielectric layer and before allocating thefirst patterned wiring layer, further comprising patterning the firstdielectric layer to form a plurality of first thru-holes, by which thefirst patterned wiring layer is electrically connected to the metal padsof the dies.
 147. The method of claim 146, wherein when allocating thefirst patterned wiring layer on top of the first dielectric layer,further comprising filling the first thru-holes with part of aconductive material of the first patterned wiring layer to form aplurality of first vias, by which the first patterned wiring layer iselectrically connected to the metal pads of the dies.
 148. The method ofclaim 146, wherein before allocating the first patterned wiring layer ontop of the first dielectric layer, further comprising filling the firstthru-holes with a conductive material to form a plurality of first vias,by which the first patterned wiring layer is electrically connected tothe metal pads of the dies.
 149. The method of claim 139, wherein amaterial of the first dielectric layer is selected from a groupconsisting of polyimide, benzocyclobutene, porous dielectric material,and stress buffer material.
 150. The method of claim 139, wherein amethod of allocating the first patterned wiring layer on the firstdielectric layer is selected from a group consisting of sputtering,electroplating, and electro-less plating.
 151. The method of claim 139,further comprising allocating a patterned passivation layer on top ofthe first dielectric layer and the first patterned wiring layer andexposing the first bonding pads.
 152. The method of claim 139, furthercomprising allocating a bonding point on the first bonding pads. 153.The method of claim 152, wherein the bonding points are selected from agroup consisting of solder balls, bumps, and pins.
 154. The method ofclaim 152, further comprising singularizing the chip package structureafter allocating the bonding point on the first bonding pads.
 155. Themethod of claim 154, wherein a singularization of the chip packagestructure is performed on a single die.
 156. The method of claim 154,wherein a singularization of the chip package structure is performed ona plurality of dies.
 157. The method of claim 139 further comprising:(a) allocating a second dielectric layer on top of the first dielectriclayer and the first patterned wiring layer; and (b) allocating a secondpatterned wiring layer on top the second dielectric layer, wherein thesecond patterned wiring layer is electrically connected to the firstpatterned wiring layer through the second dielectric layer, and thesecond patterned wiring layer extends to a region outside the activesurface of the die and has a plurality of second bonding pads.
 158. Themethod of claim 157, wherein after allocating the second dielectriclayer and before allocating the second patterned wiring layer, furthercomprising patterning the second dielectric layer to form a plurality ofsecond thru-holes, which corresponds to the first bonding pads andpenetrates the second dielectric layer, to electrically connect to thefirst patterned wiring layer.
 159. The method of claim 158, wherein whenallocating the second patterned wiring layer on top of the seconddielectric layer, further comprising filling the second thin-holes withpart of a conductive material of the second patterned wiring layer toform a plurality of second vias, by which the second patterned wiringlayer is electrically connected to the first patterned wiring layer.160. The method of claim 158, wherein before allocating the secondpatterned wiring layer on top of the second dielectric layer, furthercomprising filling the second thru-holes with a conductive material toform a plurality of second vias, by which the second patterned wiringlayer is electrically connected to the first patterned wiring layer.161. The method of claim 157, wherein a material of the seconddielectric layer is selected from a group consisting of polyimide,benzocyclobutene, porous dielectric material, and stress buffermaterial.
 162. The method of claim 157, wherein a method of allocatingthe second patterned wiring layer on the second dielectric layer isselected from a group consisting of sputtering, electroplating, andelectro-less plating.
 163. The method of claim 157, further comprisingallocating a patterned passivation layer on top of the second dielectriclayer and the second patterned wiring layer and exposing the secondbonding pads.
 164. The method of claim 157, further comprisingallocating a bonding point on the second bonding pads.
 165. The methodof claim 164, wherein the bonding points are selected from a groupconsisting of solder balls, bumps, and pins.
 166. The method of claim164, further comprising singularizing the chip package structure afterallocating the bonding point on the second bonding pads.
 167. The methodof claim 166, wherein a singularization of the chip package structure isperformed on a single die.
 168. The method of claim 166, wherein asingularization of the chip package structure is performed on aplurality of dies.
 169. The method of claim 157, further comprisingrepeating step (a) and step (b) a plurality of times.
 170. The method ofclaim 169 further comprising allocating a patterned passivation layer onthe second dielectric layer and the second patterned wiring layer thatare furthest away from the organic substrate and exposing the secondbonding pads of the second patterned wiring layer that is furthest awayfrom the organic substrate.
 171. The method of claim 169, furthercomprising allocating a bonding point on the second bonding pads of thesecond patterned wiring layer that is furthest away from the organicsubstrate.
 172. The method of claim 171, wherein the bonding points areselected from a group consisting of solder balls, bumps, and pins. 173.The method of claim 171, further comprising singularizing the chippackage structure after allocating the bonding point on the secondbonding pads.
 174. The method of claim 173, wherein a singularization ofthe chip package structure is performed on a single die.
 175. The methodof claim 173, wherein a singularization of the chip package structure isperformed on a plurality of dies.
 176. A chip package structurecomprising: an organic substrate; a die module comprising an activesurface, a backside that is opposite to the active surface, and aplurality of metal pads located on the active surface, whereas thebackside of the die module is adhered to the organic substrate; afilling layer located on top of the organic substrate and surrounding aperipheral of the die module, a top surface of the filling layer isplanar to the active surface of the die module; a thin organic layerlocated on top of the filling layer and the die module; and a thin-filmcircuit layer located on top of the thin organic layer and the diemodule and has an external circuitry, wherein the external circuitry iselectrically connected to the metal pads of the die module and extendsto a region outside the active surface of the die module, the externalcircuitry has a plurality of bonding pads located on a surface layer ofthe thin-film circuit layer and each bonding pad is electricallyconnected to a corresponding metal pad of the die module.
 177. Thestructure in claim 176, wherein the die module comprising a single die.178. The structure in claim 176, wherein the die module comprising aplurality of dies.
 179. The structure in claim 178, wherein the diesperform different functions.
 180. The structure in claim 176, wherein amaterial of the filling layer is selected from a group consisting epoxyand polymer.
 181. The structure in claim 176, wherein a thickness of thethin organic layer is in a range from about 2 microns to 200 microns.182. The structure in claim 176, wherein the die module has an internalcircuitry and a plurality of active devices located on the activesurface of the die module and the internal circuitry is electricallyconnected to the active devices, whereas the internal circuitry formsthe metal pads.
 183. The structure in claim 182, wherein a signal fromone of the active devices is transmitted to the external circuitry viathe internal circuitry, and from the external circuitry back to one ofthe active devices via the internal circuitry.
 184. The structure inclaim 183, wherein a width, length, and thickness of traces of theexternal circuitry are greater than corresponding traces of the internalcircuitry.
 185. The structure in claim 176, wherein the externalcircuitry further comprising a power/ground bus.
 186. The structure inclaim 176, wherein the thin-film circuit layer comprising at least apatterned wiring layer, which is located on the thin organic layer,whereas the patterned wiring layer is electrically connected to themetal pads of the die module through the thin organic layer and formsthe external circuitry and the bonding pads of the external circuitry.187. The structure in claim 186, wherein the thin organic layer has aplurality of thru-holes, and the patterned wiring layer is electricallyconnected to the metal pads of the die module by the thru-holes. 188.The structure in claim 187 wherein a via is located inside eachthru-hole, and the patterned wiring layer is electrically connected tothe metal pads of the die module by the vias.
 189. The structure inclaim 188, wherein the patterned wiring layer and the vias form theexternal circuitry.
 190. The structure of the claim 186, wherein theexternal circuitry further comprising at least one passive device. 191.The structure in claim 190, wherein the passive device is selected froma group consisting of a resistor, an inductor, a capacitor, awave-guide, a filter, and a micro electronic mechanical sensor (MEMS).192. The structure in claim 190, wherein the passive device is formed bya part of the patterned wiring layer.
 193. The structure in claim 176,wherein the thin-film circuit layer comprising a plurality of patternedwiring layers and a plurality of dielectric layers, in which thepatterned wiring layers and dielectric layers are alternately formed andthe patterned wiring layers are electrically connected to theneighboring patterned wiring layers through the dielectric layer, one ofthe dielectric layers is formed between the thin-film circuit layer andthe organic substrate, the patterned wiring layer that is closest to theorganic substrate is electrically connected to the metal pads of the diemodule through the dielectric layer that is closest to the organicsubstrate, where the patterned wiring layer that is furthest away fromthe organic substrate forms the bonding pads.
 194. The structure inclaim 193, wherein the thin organic layer has a plurality of firstthru-holes, by which the patterned wiring layer that is closest to theorganic substrate is electrically connected to the metal pads of the diemodule, and each dielectric layer has a plurality of second thru-holes,by which the patterned wiring layers are electrically connected to theneighboring patterned wiring layers.
 195. The structure in claim 194,wherein a first via is located inside each first thru-hole and a secondvia is located inside each second thru-hole, and each patterned wiringlayer is electrically connected to the neighboring patterned wiringlayers by the second vias, wherein the patterned wiring layer that isclosest to the organic substrate is electrically connected to the metalpads of the die module by the first vias.
 196. The structure in claim195, wherein the patterned wiring layers, the first vias, and the secondvias form the external circuitry.
 197. The structure in claim 193,wherein the external circuitry further comprising a passive device. 198.The structure in claim 197 wherein the passive device is selected from agroup consisting of a resistor, an inductor, a capacitor, a wave-guide,a filter, and a micro electronic mechanical sensor (MEMS).
 199. Thestructure in claim 193, wherein the passive device is formed by a partof the patterned wiring layer.
 200. The structure in claim 193, whereina material of the dielectric layer is selected from a group consistingof polyimide, benzocyclobutene, porous dielectric material, and stressbuffer material.
 201. The structure in claim 176 further comprising apatterned passivation layer located on top of the thin-film circuitlayer and exposing the bonding pads.
 202. The structure in claim 176further comprising a plurality of bonding points located on the bondingpads.
 203. The structure in claim 202, wherein the bonding points areselected from a group consisting of solder balls, bumps, and pins.